The increasing demand for high density magnetic recording and playback, and requirements for non-volatile memory, have focused attention on magnetic tunnel junctions, and the devices that can be prepared therefrom, such as MRAMs and the like. To date, the most advanced magnetic tunnel junctions are principally made of ferromagnetic sandwiches of thin films of aluminum oxide electron tunneling barriers between a metal which is typically iron, cobalt or nickel. Recently, crystalline magnesium oxide has been proposed as the barrier layer. Different materials are selected to improve the observed tunnel magnetic resistance values. Even with thirty (30) years of intensive investigation, the highest TMR values for the Fe/MgO/Fe are about Two Hundred Forty Percent (240%).
Graphene offers decided advantages for the tunnel barrier in a magnetic tunnel junction. Indeed, magnetic tunnel junctions (FIG. 1) composed of FM/few-layer graphene/FM stacks (FM=ferromagnet, i.e., Co, Ni) have been proposed [1] as “perfect spin” filters. The ability to form such stacks on, e.g., Cu interconnect lines would allow direct integration with Si CMOS, leading to broad new capabilities in non-volatile memory, spin-logic, and defect-tolerant, adaptive computing [2-5]. This in turn requires the ability to form multiple graphene layers on Co substrates, and to do so at temperatures below ˜700 K, the thermal stability limit of low-k dielectric materials currently employed in advanced Si CMOS devices.
Graphene growth by CVD or PVD on Co surfaces is well-reported, but is usually carried out at higher temperatures (>1000 K). Ago, et al, [9] reports the growth of ordered multilayer graphene films on Co(111)/alumina films by CVD (CH4 and H2) at >1150 K. Varykhalov and Rader [12] report the growth of epitaxial graphene on Co(0001)/W(110) by CVD of propylene at ˜730 K. Graphene films non-uniform in thickness have been grown on polycrystalline Co films by CVD (ethylene) at 1073 K [13]. To date, there has not been a satisfactory report of formation of few-layer graphene films followed by annealing to give operative devices at temperatures below 700 K.
Thus, in a typical magnetoresistive random access memory, an array of parallel first conductive lines is presented on a horizontal plane, and an array of parallel second conductive lines on a second horizontal plane is disposed above the first array in a direction perpendicular to the first array of conductive lines. See, for example, U.S. Pat. No. 7,985,579, the disclosure of which pertaining to the formation of MRAMs is incorporated herein-by-reference. The MTJ element is disposed between the two arrays at each crossover point. This requires a technology that permits formation of the stack, and annealing to operative conditions, at Si CMOS compatible temperatures to be integrated in today's dominant electronic and photonic technologies, particularly communications and computing equipment.